Flip Flops

The circuit shown below is a particular type of sequential circuit, known as a flip flop. The term “flip flop” refers to the property of these circuits such that they can flip between the binary states 0 and 1. This is done by setting the inputs appropriately. The input labelled S is used to Set the output Q to 1, where as the input labelled R is used to set the output Q to 0. These circuits will remain in the state 0 or 1 until the inputs are changed to the opposite settings. Hence these circuits are widely used as memory devices as they can store information indefinitely and they can be Set and Reset by the system. Note that in the following animation the input R=1, S= 1 is not allowed as it can cause the circuit to enter an invalid state

The clock signal is commonly added to logic circuits by way of an AND gate. We know from Boolean algebra that 0·X=0 and 1·X=X. Hence if the clock is 0, then the output of the AND gate is always 0; if the clock if 1 then the output of the AND gate is whatever X is. The invalid input can be avoided by modifying this circuit as follows

However the unstable state can be accounted for by redesigning the flip flop so that the behaviour of the circuit is defined for the unstable inputs. This is known as a JK flip flop. The initials J and K are from the German words for Set and Clear. The JK flip flop can be constructed as follows:

In the last circuit we saw that the output may change when the clock is set to 1. However, the clock must be set to 1 for a minimum amount of time in order for the information to flow through the circuit. If the clock is not on for the minimum amount of time then the input will not propagate through the circuit. Moreover, if the clock is left on for too long a time then the output may change too often. The timing of this clock signal can be extremely difficult to control, when one considers that the clock signal may be 1 Giga Hertz, which means that one pulse lasts for only 1 billionth of a second!

This timing problem can be overcome if we make the flip flop sensitive to the pulse transition, rather than the pulse length. Such a circuit is known as a pulse triggered flip flop. One example of a pulse triggered flip flop is the Master-Slave flip flop. This can be formed by connecting two JK flip flops in the following fashion. Drag the red slider in the clock in the following animation to increase/decrease the clock rate:

from: http://www.pwalsh.net/cs/flipflops.htm